Method and module for processing ATM cells in bidirectional data streams

ABSTRACT

For processing ATM cells in bidirectional, upstream and downstream data streams in an ATM module, whereby the processing speed is higher than the average cell rate and empty cycles without ATM cells occur in the cell stream, a processing logic of the module—for the purpose of an alternating processing of upstream or downstream cells—makes requests upstream and downstream for empty cycles to an empty cycle controller in order to receive processing time. The cells of the downstream data stream can be separately backed up and released in a buffer and, in this way, downstream empty cycles can be generated. Given a downstream empty cycle request, this request is allowed with priority over a simultaneous downstream request when an empty cycle occurs, and, given a downstream empty cycle request, an empty cycle is released delayed by one cycle length if an upstream request is simultaneously present but is otherwise immediately released.

BACKGROUND OF THE INVENTION

The present invention is directed to a method for processing ATM cellsin bidirectional modules processing upstream and downstream data streamsin messages, whereby the processing speed is higher than the averagecell rate and empty cycles without ATM cells occur in the cell stream.

The present invention is also directed to a module for processing ATMcells in bidirectional, upstream and downstream data streams, forexample an OAM module, having inputs and outputs and interfaces for theupstream and the downstream data stream, having an upstream cellprocessing unit and having a downstream cell processing unit as well ashaving a processing logic.

ATM, the abbreviation for “Asynchronous Transfer Mode”, is a networktechnology that is suitable for the transport of all known signal datasuch as pure data, voice and video data, etc., whereby the designationATM is occasionally employed as a synonym for B-ISDN (BroadbandIntegrated Services Digital Network). A structuring into cells of equallength is characteristic of ATM. The information to be communicated isdivided onto ATM cells, namely into packets of 53 bytes, that carry acell header of 5 bytes and payload information of 48 bytes. The headerinformation thereby identifies a specific virtual connection. Bycontrast to traditional time-division multiplex methods, wherein timeslots are allocated in advance to various types of data traffic, thedata traffic incoming at an ATM interface is segmented into said 53-bytecells, and these cells are sequentially forwarded as they weregenerated. Further details regarding ATM can be derived from theliterature. See for example: “ATM-Networks, Concepts, Protocols andApplications”, Handel, Huber and Schroder, Addison-Wesley-Longman,Second Edition, 1994 (ISBN 0-201-42274-3).

Highly integrated circuits in ASIC modules are employed for processingATM cells. OAM cells are one example, these being utilized for theadministration and processing of the OAM streams (OAM=OperationAdministration and Maintenance). OAM modules or other cell processingmodules are utilized, for example, between network matching units and aswitching network module or other modules. FIG. 1 is referenced withrespect thereto, this showing a possible architecture. Physical layermodules PHY can be seen at the left and right in the figure, theseenabling the transition from a transport network, for example STM1, ontoATM. The dot-dashed lines at the left and right symbolize the boundariesbetween the physical layer Phy.L and the ATM layer ATM-L. ATM modulesBST are provided symmetrically relative to a switching network moduleSWI, these lying between the switching network module SWI and thephysical layer modules PHY. Dependent on the demands and conditions, oneor more ATM modules BST can be present. In order to indicate this, arespective ATM module is shown with broken lines.

As can be derived from the block circuit diagram according to FIG. 1,which is relevant both for the prior art as well as for the invention,bidirectional data streams are processed, these being referenced UP forupstream and DOWM for downstream. The designations upstream anddownstream indicate the direction “up to” the switching network or,“down from” the switching network given switching networks. Basically,the designations of the two data streams as UP and DOWN, however, arearbitrary and interchangeable with one another.

Separate ATM modules can be employed for the processing of the cells ofthe two data streams or—as shown in FIG. 1, both data streams can beprocessed in one ATM module. This is the relevant case here. In theprior art, the gate logic required for the cell processing is therebydoubly implemented in order, namely, to be able to process each of thetwo data streams.

It is object of the invention to provide a savings in terms of hardware,namely in terms of gate area of the modules, given employment of ATMmodules for bidirectional data streams.

SUMMARY OF THE INVENTION

This object is inventively achieved in accordance with the presentinvention in a method for processing ATM cells in bidirectional,upstream and downstream data streams in messages, wherein the processingis performed in modules each having a processing logic at a processingspeed higher than an average cell rate, the upstream and downstream datastreams having occurrences of empty cycles without ATM cells, in thatthe processing logic of the module—for the purpose of an alternatingprocessing of upstream or, downstream cells—makes upstream anddownstream demands for empty cells in order to obtain processing time,the cells of the downstream data stream can be separately backed up andreleased and, in this way, downstream empty cells can be generated,whereby, given an upstream empty cycle demand in the case of a emptycycle that has occurred, this demand is allowed with priority over asimultaneous downstream demand, and, given a downstream empty cycledemand, a empty cycle is released delayed by a cycle length if anupstream demand is simultaneously present, but is otherwise immediatelyreleased.

The object is likewise achieved in accordance with the present inventionin a module having a processing logic for processing ATM cells inbidirectional, upstream and downstream data streams in messages, whereinthe processing is performed at a processing speed higher than an averagecell rate, the upstream and downstream data streams having occurrencesof empty cycles without ATM cells, whereby, according to the invention,an empty cycle controller is provided, the processing logic isconfigured—for the purpose of an alternating processing of upstream or,respectively, downstream cells—to send requests for empty cycles to theempty cycle controller, the downstream entry interface is configured tobackup and release the cells of the data stream in controlled fashionand, in this way, to generate downstream empty cycles, and the emptycycle controller, which is provided by the entry interface of theupstream data stream with information about occurring upstream emptycycles, is configured, given an upstream empty cycle request, to allowthis request with priority over a simultaneous downstream request whenan empty cycle occurs, to send an instruction—given a downstream emptycycle request—to the downstream entry interface for a release delayed bya cycle length when an upstream empty cycle request is simultaneouslypresent but otherwise a command for immediate release.

The present invention utilizes the fact that empty cells having astatistical source occur in ATM systems. Given involvement of aswitching network, this is the case in the cell stream UP, namely due toan elevated bit rate, since ATM cells are processed faster in an ATMmodule than the resupply of ATM cells. There is thus a probabilitydependent on the input bit rate and on the processing speed in themodule that no ATM cell will be located in an input buffer for one ofthe two cell streams. In the other cell stream—always the “downstream”cell stream DOWM, for example, below empty cells are actively generatedas a result of the backing up of the ATM cells defined by the module, inthat no ATM cell is allowed downstream in the input buffer, so that acell gap, i.e. an empty cell, arises. As a result thereof and bycoordinating the empty cells upstream or, downstream, many functions canbe processed upstream or, downstream by a single logic in alternation inthe cell stream, so that these logic parts need be implemented only oncein a module and gate area is saved.

It is expedient when selected functions such as, for example, “internalRAM update”, are processed in alternation during empty cycles.

Particularly when access to external buffers is difficult, it can beexpedient when a backup buffer for the downstream data stream isprovided preceding the downstream processing unit, this beingcontrollable by the processing logic via the empty cycle controller.

These and other features of the invention(s) will become clearer withreference to the following detailed description of the presentlypreferred embodiments and accompanied drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block circuit diagram of a general ATM structure with aswitching network module.

FIG. 2 is a block circuit diagram of a module constructed and operatedin accordance with the present invention.

FIG. 3 shows an example of a flowchart for the implementation of themethod of the present invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

FIG. 1 was already referenced at the outset in conjunction with anexemplary ATM structure. FIG. 2 then shows one of the ATM modules BSTshown in FIG. 1. The module BST is configured for processingbidirectional data streams, namely a data stream UP and a data streamDOWN, whereby the input or, output interface for the data stream UP isreferenced SUI or respectively SUO, and the input or output interfacefor the data stream DOWN is referenced SDI or SDO. The input interfaceSDI of the “downstream” data stream DOWN has a controllable, internalbuffer BUF allocated to it in this embodiment; however, it should bepointed out that such buffers, which can back up cells, are usuallyavailable outside the module BST.

Further, the module BST has an upstream cell processing unit ZVU as wellas a downstream cell processing unit ZVD. Such a cell processing unithas a buffer function; by analogy it forms a “workbench” on which theretained cell can be processed. These processing units ZVU, ZVD servethe purpose of cell processing in view of all jobs that are to beimplemented simultaneously and clocked.

The module BST also contains a processing logic VAL for those jobs ofcell processing that are not bound in time to simultaneous cellprocessing. The cell processing is quite generally triggered by a cellprocessing start signal that fundamentally corresponds to the signal“empty cycle occurred”, i.e. “no cell occurred”, and that comes upstreamfrom the interface SUI. The processing logic VAL is in communicationwith an empty cycle controller LZS that in turn receives signals aboutthe presence of empty cells in the upstream cell stream UP from theupstream input interface SUI and, on the other hand, can deliver controlsignals to the downstream cell processing unit ZVD as well as to theinternal backup buffer BUF or to an external buffer. This is explainedin greater detail below.

It is assumed below that the processing of the cells after the interfaceSUI of the upstream cell stream UP ensues faster than cells areresupplied. This assumption is indispensable, on the one hand, for thefunctioning of a cell processing because, given the contrary case, acell backup with memory overflow and cell loss would occur and, on theother hand, it results in the occurrence of cell gaps or empty cycleshaving a length corresponding to the respective cell length.

The statistically occurring empty cycles in the cell stream UP are notinfluenced; rather, they are accepted or employed as they occur. Theyare, so to speak, assigned a priority. By contrast thereto, empty cyclesin the downstream cell stream DOWN are activated by the module. Thisensues by the backup of the ATM cells defined by the module. When thebuffer BUF—or, alternatively, the input interface SDI of the downstreamcell stream DOWM—receives a command to block the cell stream for a celllength, an empty cell occurs as a result.

The logic VAL is then configured, in conformity with the pendingprocessing jobs, to make empty cycle demands upstream or downstream ofthe empty cycle controller LZS, this being indicated in FIG. 2 with thearrows “EC up Req” or “EC down Req”. The occurrence of empty cycles inthe upstream cell stream UP is thereby reported from the input interfaceSUI to the empty cycle controller LZS with a signal “EC up”. The commandfor empty cycle generation downstream, referenced “EC down” in FIG. 2,proceeds from the empty cycle controller LZS to the backup buffer BUF.Corresponding messages, of course, also proceed to the two cellprocessing units ZVU and ZVD. The empty cell controller LZS sendsacknowledgment signals “EC up Ack” and “EC down Ack” to the processinglogic VAL that serves for the alternating cell processing upstream anddownstream. The module is also fundamentally additionally configured fora simultaneous processing of the cells upstream and downstream in viewof functions that require such a processing or it could contain what isreferred to as a “cross channel” in order to reroute cells from datastream into the other; details about this, however, are not requiredsince they do not affect the invention. What is critical here is thatjobs are implemented in the empty cycles that are not bound in terms oftime to the simultaneous and clocked cell processing.

As already mentioned, an empty cycle request upstream is allowed insofaras an empty cycle has statistically occurred upstream. There is anexception when a downstream empty cycle request already pending wasdelayed due to the upstream empty cycle request that has higherpriority. The empty cell request downstream is delayed maximally by thelength of one empty cell, i.e. the downstream empty cycle is activelygenerated no later than one such cell length following the request. Inthis special case, an empty cycle upstream that could at most again bepresent is “given away”.

This procedure is necessary since, given a high plurality of emptycycles occurring upstream, for example given a low cell rate at theinput upstream, the empty cell requests downstream would otherwise bedelayed unnecessarily long and, in the extreme case when, namely, thecell rate at the upstream input is zero, could not be implemented atall.

If there is no conflict between empty cycle requests upstream anddownstream, the empty cycle request upstream is allowed as soon as astatistically empty cycle occurs upstream. The empty cell requestdownstream is immediately allowed, since the empty cycle downstream canbe activated in the module itself.

The method explained above with reference to the presentation of themodule BST is explained again by the flowchart of FIG. 3. In thisflowchart, the above-described instances can be logically seen, forexample the delay of a downstream empty cycle, referenced “EC downdelay” in the flowchart. The designation EC (empty cycle) isconsistently employed for “empty cycle” in the flowchart and theabbreviation Req stands for “request”. Moreover, the flowchart isself-explanatory, so that no further explanation is required.

Although modifications and changes may be suggested by those of ordinaryskill in the art, it is the intention of the inventors to embody withinthe patent warranted hereon all changes and modifications as reasonablyand properly come within the scope of their contribution to the art.

What is claimed is:
 1. A method for processing ATM cells inbidirectional, upstream and downstream data streams in messages, whereinsaid processing is performed in modules each having a processing logicat a processing speed higher than an average cell rate, said upstreamand downstream data streams having occurrences of empty cycles withoutATM cells, said method comprising the steps of: alternating processingof cells of said upstream and downstream data streams by making upstreamand downstream requests for empty cycles in order to receive aprocessing time; generating downstream empty cycles by separatelybacking up and releasing cells of said downstream data stream; allowingan upstream empty cycle request with priority over a simultaneousdownstream empty cycle request given an occurring upstream empty cycle;releasing a downstream empty cycle delayed by a cycle length given adownstream empty cycle request and a simultaneous upstream empty cyclerequest and no occurring upstream empty cycle; and releasing adownstream empty cycle immediately given a downstream empty cyclerequest and no simultaneous upstream empty cycle request.
 2. The methodaccording to claim 1, wherein selected functions are processed inalternation during upstream and downstream empty cycles.
 3. A module forprocessing ATM cells in bidirectional, upstream and downstream datastreams, said module comprising: an upstream input interface forreceiving said upstream data stream, said upstream input interfaceoutputting information about occurring upstream empty cycles; adownstream input interface for receiving said downstream data stream,said downstream input interface for delaying and releasing cells of saiddownstream data stream in a controlled fashion and for therebygenerating downstream empty cycles; an upstream output interface foroutputting said upstream data stream; a downstream output interface foroutputting said downstream data stream; an upstream cell processing unitconnected between said upstream input interface and said upstream outputinterface; a downstream cell processing unit connected between saiddownstream input interface and said downstream output interface; aprocessing logic for alternating processing of upstream cells anddownstream cells and for outputting upstream empty cycle requests anddownstream empty cycle requests; and an empty cell controller forreceiving information about occurring upstream empty cycles from saidupstream input interface and for receiving upstream empty cycle requestsand downstream empty cycle requests from said processing logic, saidempty cell controller allowing with priority a received upstream emptycycle request over a simultaneously received downstream empty cyclerequest given an occurring upstream empty cycle, said empty cellcontroller sending to said downstream input interface a command for arelease delayed by a cycle length given a downstream empty cycle requestand a simultaneous upstream empty cycle request and no occurringupstream empty cycle, said empty cell controller sending to saiddownstream input interface a command for immediate release given adownstream empty cycle request and not a simultaneous upstream emptycycle request.
 4. The module according to claim 3, further comprising: abackup buffer preceding said downstream cell processing unit and forbuffering said downstream data stream, said backup buffer beingcontrolled by said processing logic via said empty cycle controller.